In general, vias are vertical pathways to electrically connect a first metal layer to a second metal layer in a semiconductor device. A super via is vertical pathway which spans more than one metal layer, such as, for example, a via which spans two metal layers, and does not include a landing pad on an intermediate metal layer. Conventional methods for manufacturing super vias result in necking portions, where middle portions of the super vias have a reduced width compared with that of overlaying and underlying portions of the super via. For example, a necking profile can occur during formation of a super via at a location corresponding to a transition between dielectric materials of two different interconnect levels. The necking profile can be due to a capping layer between two dielectric layers of different interconnect levels having a slower etch rate than the dielectric layers during a reactive ion etch (ME) process to form the super via. The slower etch rate of the capping layer causes the reduced width of that portion.
In addition, conventional methods for forming vias or super vias do not maintain sufficient control over via or super via critical dimensions (CDs), especially when etching dielectric layers (e.g., ultra-low K (ULK) dielectric layers). Since increased chip density leads to via and interconnect distance being relatively close, shorts can occur between vias and interconnects when via or super via CDs are too large due to over-etching of dielectric layers. For example, top portions of vias and super vias in 10 nm node typically have larger CDs than the bottom portions, resulting in top CDs, which are out of specification.
Accordingly, there is a need for methods and structures which prevent overly large CDs in vias and super vias, and necking profiles in super vias.